Ferroelectric random access memory (FRAM) devices are "nonvolatile" memory devices because they preserve data stored therein even in the absence of a power supply signal. The nonvolatile nature of a ferroelectric memory cell is a direct consequence of using a ferroelectric material as the dielectric of the cell's capacitor. Typical ferroelectric materials which can be used for the ferroelectric capacitor include Phase III potassium nitrate, bismuth titanate and lead zirconate titanate Pb(Zr, Ti)O.sub.3 (PZT). Because these ferroelectric materials possess hysteresis characteristics, the polarity (i.e., state) of the ferroelectric material can be maintained even after interruption of the power supply. Thus, data (e.g., logic 0,1) can be stored in the FRAM as the polarity state of the ferroelectric material in each capacitor.
FRAM devices may typically be classified into two categories. In the first category, the gate insulating film of a field effect transistor comprises a ferroelectric material. In the second category, a field effect access transistor and a ferroelectric capacitor are provided as part of a unit cell. Unfortunately, the electrical characteristics of FRAM devices from the first category may suffer if the lattice constants or thermal expansion coefficients between a silicon substrate and the ferroelectric gate insulating film are significantly different. However, FRAM devices in the second category typically do not suffer from such limitations on performance.
Referring now to FIG. 1, a typical FRAM device from the second category includes a field effect access transistor having a gate G, source S and drain D which are electrically coupled to a word line W/L, second electrode of a ferroelectric capacitor C.sub.F and a bit line B/L, respectively. A plate line P/L is also electrically connected to a first electrode of the ferroelectric capacitor C.sub.F. As illustrated by FIG. 2, the conventional FRAM device of FIG. 1 includes a source region 9 and a drain region 11 which are formed in a semiconductor substrate 1 of first conductivity type (e.g., P-type). A field oxide isolation region 3 is also provided in the substrate 1. The access transistor also includes a gate oxide layer 5 and a gate electrode 7 which is electrically coupled in common to other gate electrodes as a word line W/L. First and second borophosphosilicate glass (BPSG) layers 13 and 19 are also provided. A bit line 23 is also provided. The bit line 23 extends through the first and second BPSG layers, as illustrated. An upper electrode 21 of the ferroelectric capacitor is electrically connected to the source region 9. The lower electrode 15 and ferroelectric dielectric layer IS of the ferroelectric capacitor are provided on the first BPSG layer 13. The lower electrode and upper electrode of the ferroelectric capacitor may comprise platinum and the ferroelectric dielectric layer may comprise PZT.
Notwithstanding the above-described nonvolatile integrated circuit memory devices, there continues to be a need for more highly integrated nonvolatile memory devices (e.g., FRAM devices) and methods of forming these memory devices using simplified and economical fabrication techniques.